module top
       (
           input rst_n,
           input clk,
           input [7: 0] in_data,
           output reg [15: 0] out_data
       );

reg [15: 0] last_data0, last_data1;
reg [7: 0] cnt;

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				out_data <= 0;
				cnt <= 1;
			end
		else if (cnt < in_data)
			begin
				cnt <= cnt + 1'b1;
			end
		else if (cnt == in_data)
			begin
				out_data <= last_data1;
				cnt <= cnt;
			end
		else if (cnt > in_data)
			begin
				cnt <= 16'd1;
			end
		else
			begin
				out_data <= out_data;
			end
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n || cnt > in_data)
			begin
				last_data0 <= 16'd1;
				last_data1 <= 16'd1;
			end
		else if (cnt < in_data)
			begin
				last_data1 <= last_data0;
				last_data0 <= last_data1 + last_data0;
			end
		else
			begin
				last_data1 <= last_data1;
				last_data0 <= last_data0;
			end
	end
endmodule

